Lectures

1. Introduction

1. B. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning of Electrical Circuits", Bell System Technical Journal", pp 291-307, 1970. (pdf)
2. C. M. Fiduccia and R. M. Mattheyses. "A linear-time heuristic for improving network partitions", Proceedings of the Design Automation Conference, pp 174-181, 1982. (pdf)
3. L. Hagen and A. B. Kahng, "New Spectral Methods for Ratio Cut Partitioning and Clustering", IEEE Trans. on Computer-Aided Design, 11(9), pp 1074-1085, 1992. (pdf)
4. H. Yang and D. F. Wong, "Efficient Network Flow Based Min-cut Balanced Partitioning", IEEE Trans. on Computer-Aided Design, 15(12), pp 1533-1540, 1996. (pdf)

1. R. Rajaraman and D. F. Wong, "Optimal Clustering for Delay Minimization", IEEE Trans. on Computer-Aided Design, 14(1), pp 1074-1085, 1992. (pdf)
2. J. Cong and Y. Ding, "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design, 13(1), pp 1-12, 1994. (pdf)
3. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, "Multilevel Hypergraph Partitioning: Application in VLSI Domain", IEEE Trans. on VLSI, 7(1), pp 69-79, 1999. (pdf)

1. L. Stockmeyer, "Optimal Orientation of Cells in Slicing Floorplan Designs", 57(2-3), Information and Control, pp 91-101, 1984. (pdf)
2. D. F. Wong and C. L. Liu, "Floorplan design of VLSI circuits", Algorithmica, 4(1), pp 263-291, 1989. (pdf)
3. S. Sutanthavibul, E. Shragowitz, and J. Rosen, "An analytical approach to floorplan design and optimization", IEEE Trans. on Computer-Aided Design, 10(6), pp 761-769, 1991. (pdf)
4. H. Murata, K. Fujiyoshi, S. Nakatake and Y. Kajitani, "VLSI module placement based on rectangle-packing by the sequence-pair", IEEE Trans. on Computer-Aided Design, 15(12), pp 1518-1524, 1996. (pdf)

1. M. Breuer, "A Class of Min-cut Placement Algorithms", Proceedings of the Design Automation Conference, pp 284-290, 1977. (pdf)
2. A. Dunlop and B. Kernighan, "A Procedure For Placement Of Standard-cell VLSI Circuits", IEEE Trans. on Computer-Aided Design, 4(1), pp 92-98, 1985. (pdf)
3. J. Kleinhaus, G. Sigl, F. Johannes, K. Antreich, "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization", IEEE Trans. on Computer-Aided Design, 10(3), pp 356-365, 1991. (pdf)
4. W. J. Sun and C. Sechen, "Efficient and Effective Placement for Very Large Circuits", IEEE Trans. on Computer-Aided Design, 14(3), pp 349-359, 1995. (pdf)

1. J. M. Ho, G. Vijayan, and C. K. Wong, "New algorithms for the rectilinear Steiner tree problem", 9(2), IEEE Trans. on Computer-Aided Design, pp 185-193, 1990. (pdf)
2. A.B. Kahng and G. Robins, "A new class of iterative Steiner tree heuristics with good performance", IEEE Trans. on Computer-Aided Design, 11(7), pp 893-902, 1992. (pdf)
3. M. Borah, R. Owens, and M. Irwin, "An Edge-based Heuristic for Steiner Routing", IEEE Trans. on Computer-Aided Design, 13(12), pp 1563-1568, 1994. (pdf)
4. J. Cong, A.B. Kahng, G. Robins, M. Sarrafzadeh, and C.K. Wong, "Provably good performance-driven global routing", IEEE Trans. on Computer-Aided Design, 11(6), pp 739-752, 1992. (pdf)
5. J. Cong, K.-S. Leung, and D. Zhou "Performance-Driven Interconnect Design Based on Distributed RC Delay Model", UCLA CSD Tech Report #9200043, 1992. (pdf)
6. K. Boese, A. B. Kahng, B. McCoy, and G. Robins, "Near-optimal critical sink routing tree constructions", IEEE Trans. on Computer-Aided Design, 14(12), pp 1417-1436, 1995. (pdf)

1. C. Chiang and M. Sarrafzadeh, "Global routing based on Steiner min-max trees", IEEE Trans. on Computer-Aided Design, 9(12), pp 1318-1325, 1990. (pdf)
2. E. Shragowitz and S. Keel, "A global router based on a multicommodity flow model", Integration, the VLSl Journal, 5(1), pp 3-16, 1987. (pdf)
3. J. Cong and B. Preas, "A new algorithm for standard cell global routing", Integration, the VLSI Journal, 14(1), pp 49-65, 1992. (pdf)
4. T. Yoshimura and E. Kuh, "Efficient Algorithms for Channel Routing", IEEE Trans. on Computer-Aided Design, 1(1), pp 25-35, 1982. (pdf)