I. Setup for Cadence SoC Encounter

1. Copy the following files into your working directory.
   • gscl45nm.lef
   • gscl45nm.tlf
   • gscl45nm.map
   • test.v

2. Type the following command to source the designated file.
   • source /tools/linsoft2/cadence/edi91hf05/cshrc.edi9

3. Run Cadence SoC Encounter by typing 'encounter'. Do not use background command (= 'encounter &').

4. Cadence SoC Encounter manual provided by Cadence can be found in the following directory.

   /tools/linsoft2/cadence/edi91hf05/doc/encounter/encounter.pdf

II. Placement and Routing

1. Importing your design
   
   1. Click 'Design' and choose 'Design Import...'.

      

   2. Click the button '1', click the open button in 'Netlist Files' window, add your netlist file (test.v) by double-clicking, and close the 'Netlist Files' window.

      

   3. Click the button '2' to make Encounter find the top cell automatically.

   4. Click the button '3', click the open button in 'Timing Files' window, add 'gscl45nm.tlf' by double-clicking, and close the 'Timing Files' window.

      

   5. Click the button '4', click the open button in 'LEF Files' window, add 'gscl45nm.lef' by double-clicking, and close the 'LEF Files' window.

      

   6. Your 'Design Import' window should look like the following.

      

   7. Click 'OK' to import your design. Look at your command shell window. Encounter shows various information while it imports the design. The main window of Encounter will show you rows, where standard cells will be placed during placement.

2. Setting up layout area
   In this step, we will set up layout area. We will not do floorplanning.

   1. Choose 'Floorplan' and then 'Specify Floorplan ...' in the main window

   2. In 'Basic' tab, you can specify core size by (1) AR (Aspect Ratio) or (2) Dimension. 'Core' is the region that cells are placed.

   3. Choose 'Dimension' under 'Core Size by', and set width and height to be 100. (100 by 100 is actually too large for this design. You will be asked to change the width and height later.)

   4. Choose 'Core to IO Boundary' and set 'Core to Left', 'Core to Top', 'Core to Right' and 'Core to Bottom' to 5

   5. Click 'OK' to finish and see the modified floorplan outline in the main window. It should look like the following.

      

3. Placement options
   There is 'Place' menu in the menu bar but we will not use it because placement results done by clicking the menu are weird. Instead, we will use command shell window to do placement. However, you need to know what kind of options you have for placement.

   1. Choose 'Place' -> 'Standard Cells And Blocks' then you will see the following window.

      

   2. Click 'Advanced Tab' and see 'Perform Congestion Optimization' and 'Specify Maximum Routing Layer' options. We will use these two options as well as the options in 'Basic Tab'.

   3. Click 'Cancel' to close the window. Do not click 'OK' or 'Apply'.

4. Performing placement
   Now, go to your command shell window.

   1. In the prompt, type
      • setPlaceMode -timingdriven -reorderScan -congMediumEffort -doCongOpt -modulePlan
      • amoebaplace

   2. Encounter will do placement. After placement is done, click 'Physical view' button in the main window and see how standard cells were placed. The following figure shows an example

      

   3. In the physical view, click any cell and see the information of the cell in the bottom-right part of your window.

   4. To see the core utilization, click '%' button in the toolbar and drag and make a rectangle containing the core region. The utilization will be shown in your command shell window. It will be about 25% in this example.

5. Performing routing
   
   1. Choose 'Route' -> 'Nanoroute' -> 'Route...' then you will see the following window.

      

   2. Click 'OK' to do routing with default settings. Click 'Physical view' button and see the routing result. It should look like the following.

      

   3. See your command shell window. It shows the routing information such as total wirelength, total wirelength in each metal layer, the number of vias, the number of DRC violations, and so on.

   4. How to capture screenshots: Choose 'Tools' -> 'Dump To GIF File...'

6. How to view specific metal layers and vias
   
   1. Click the following small bar in the main window.

      

   2. Scroll down and see the following items.

      

   3. You can turn on and off the visibilities of metal layers and vias. Turn on and off visibilities and see if it works well. You will need this to capture specific metal layers later.

III. GDSII File Generation

1. Choose 'Design' -> 'Save' -> 'GDS...' then you will see the following window.

   

2. Use the following setting:
   • Output Stream File : type a file name for gdsii output file.
   • Map File : choose 'gscl45nm.map'
   • Library Name : test (for test.v), IC1 (for IC1.v), IC2 (for IC2.v), IC3 (for IC3.v)
   • GDS Structure Name : same as Library Name

3. The GDS Export window should look like the following.

   

   Click 'OK' to save your design.

IV. Exercise

1. Try the whole step with the same netlist file (test.v) and the modified core area (30x30). You don't need to turn off and on Encounter. Just start from '2.2 setting-up of layout area' step. After placement is done, check out your command shell window. You will see error messages because core area is too small.

2. Try the whole step with the same netlist file with the modified core area (N by N). At this time, try with various N values and find the minimum N which passes placement and routing without any error.

3. Add '-maxRouteLayer 4' in your setPlaceMode command during placement as follows.
   setPlaceMode -timingdriven -reorderScan -congMediumEffort -doCongOpt -modulePlan -maxRouteLater 4

   Run 'amoebaplace'. After placement is done, open NanoRoute window and see 'Top Layer' in 'Routing Control' box. The value in 'Top Layer' box should be 4 which you specified during placement. Run nanoroute and see the number of metal layers used in routing in your command shell window.