A way to design ICs in short development time is to use high-level languages which have been developed for IC design. These languages are called HDL (Hardware Description Language). VHDL and Verilog are two representative HDLs.
The source files written with HDLs are then compiled and converted into netlists. This process is called synthesis. Netlists contain cells (gates) and nets. Nets are wires which connect cells. Cells come from standard cell libraries which are made by circuit designers and include complex cells such as full adder, as well as simple cells such as NAND and NOR.
Netlists are then brought into physical design level which is done on silicon to make layouts. In this step, we do floorplanning, placement and routing. Floorplanning places blocks, which are sets of cells, on silicon. Floorplanning is followed by placement which places standard cells. After placement, nets are routed automatically by routers. Power planning (routing of power/ground nets) and clock network synthesis (routing of clock nets) are also done before/after/during routing.
The final result is converted into gdsii format. This file is tested for DRC (Design Rule Checking), LVS (Layout Versus Schematic), SPICE simulation, and so on.