Professor
School of Electrical and Computer Engineering, Georgia Institute of Technology
Associate Editor, IEEE Design & Test of Computers

My projects (selected) DARPA ERI, 3DSOC My awards (selected) Class of 1940 Course Survey Teaching Effectiveness Award (Institute-level Teaching Award based on Student Course Survey): 2016, 2018, 2019, 2020. My chips The world's first many-core 3D IC from academia: The 3D-MAPS Processors My media coverage (selected) Nvidia R&D chief sketches road to chip stacks: EE Times (Mar 2013) The Rise of the Monolithic 3-D Chip: IEEE Spectrum (Feb 2014) Qualcomm Calls for Monolithic 3D IC: EE Times (Jun 2014) Carbon nanotube Transistors Go Head-to-Head With Silicon: IEEE Spectrum (Jan 2015) Four Challenges in Teaching Grad-Level Physical Design: Cadence (May 2016) 2D tools adapt to create smaller monolithic 3DIC designs: Tech Design Forum (June 2016) GlobalFoundries, Arm Close in on 3D Chip Integration: IEEE Spectrun (Aug 2019) Stacking Memory On Logic, Take Two: Semiconductor Engineering (Sep 2019) My books (selected) Practical Problems in VLSI Physical Design Automation (2008, Springer): available at Springer and Amazon (resource website, book review) Design for High Performance, Low Power, and Reliable 3D Integrated Circuits (2013, Springer): available at Springer and Amazon (DAC 2013 #1 seller) Other info My curriculum vitae GT-KAIST Dual BS/MS Programs